1. Technical Field
This invention generally relates to fabrication of integrated circuit capacitors, and more specifically relates to fabrication of on-chip capacitors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced without loss of device performance.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) markets. One particular area of concern in DRAM design is the storage capacitor used to store each memory cell. The density of DRAM designs is to a great extent limited to by the feature size of the storage capacitor.
A charge stored in a storage capacitor is subject to current leakage and, therefore, DRAM must be refreshed periodically. The time allowed between refresh without excess charge leakage is the xe2x80x9cdata retention timexe2x80x9d, which is determined by the amount of charge stored at the beginning of the storage cycle and the amount of leakage current through different kinds of leakage mechanisms. Many efforts are expended to minimize the leakage mechanisms so as to extend the time allowed between refresh cycles.
Several methods have been used to facilitate the shrinkage of the capacitor feature size while maintaining sufficient capacitance. For example, stacked capacitors have been located above the transfer devices. Unfortunately, this approach presents difficulties with topography and with connecting the capacitors.
Another approach has been the use of trench capacitors as storage capacitors. Trench capacitors extend the storage node into the substrate to increase the capacitance without increasing the area used on the substrate. The trench capacitor design conventionally uses a highly conductive single crystal silicon substrate as the counter electrode, and a highly conductive polycrystalline silicon in a deep trench as the storage electrode of the capacitor. By extending the capacitor in the vertical dimension, trench capacitors allow the capacitor feature size to be decreased without decreasing the resulting capacitance. Capacitance for a trench capacitor is described by the following equation:   C  =      K    xc3x97                  A        trench                    T        film            
Where C is capacitance, K is the dielectric constant of the node dielectric layer, Atrench the sidewall area of the trench, and Tfilm is the thickness of the node dielectric film. As described by the previous equation, the capacitance of a trench capacitor is linearly dependent upon the sidewall area of the trench and the dielectric constant of the node dielectric layer, and inversely dependent upon the thickness of the dielectric film.
Traditionally, as the trench area decreases, the capacitance has been maintained by decreasing the thickness of the dielectric film. However, a fundamental thickness limit is being approached due to the leakage currents through the dielectric film as it is being thinned. The leakage currents across the n ode dielectric must be low enough that the stored charge, which delineates either a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d bit state, remains long enough to be detected at a later time. The tunneling currents are exponentially dependent upon the thickness of the node dielectric layer and the barrier height between the electrode material and the node dielectric layer. Thinning the node dielectric layer causes an exponential increase in leakage current, placing a limit on how much the node dielectric can be thinned. Therefore, the capacitor performance is defined as a capacitance at a specified leakage or a leakage current at a specified capacitance. The higher the capacitance at a specified leakage current, the higher is the performance of the capacitor. Similarly, the lower the leakage current at a specified capacitance, the higher is the performance of the capacitor.
Metal-Insulator-Semiconductor (MIS) structures are often employed in advanced field effect transistors (FET). They have also been optimized in the capacitance and leakage space. The art of making short-channel FETs teaches that the insulator layer in an MIS structure should be ultra thin (less than 20 xc3x85 for the current generation of high performance MOSFETs) in order to suppress short-channel effects and increase the performance of the transistor.
It is customary to measure the thickness of a gate insulator in terms of an equivalent silicon oxide thickness (EOT). The FOT of the dielectric is simply a measure of its capacitance per unit area. When silicon oxide is used as the dielectric of a capacitor, its EOT is close to its physical thickness. Accordingly, from the stand point of advanced MIS FET transistors, it is desirable to have a gate insulator with an EOT of below 20 xc3x85. A fundamental parameter that limits the physical thickness of a gate insulator and, consequently, its EOT, is the leakage current through a thin dielectric. High-performance FETs in logic circuits require a gate leakage current of less than 1-10 A/cm2. Accordingly, gate insulators are selected, in-part, on the basis of their EOT and a leakage current of less than 1-10 A/cm2. A quality factor for a gate insulator includes long-term reliability parameters, interface trap density, and fixed mobile charge.
Contrarily, high-performance capacitors have an entirely different set of parameters even though some of them are MIS structures. For a typical DRAM capacitor, the leakage current should be below 10xe2x88x927 A/cm2in order to retain the stored charge for several milliseconds. In addition, capacitors are not sensitive to the interface charge density. This allows for the use of a wide variety of dielectric materials in a capacitor which are not suitable for gate insulators due to the density of interfacial traps. Accordingly, the present disclosure relating to on-chip capacitors is different from the art of thin gate insulators due to the different requirement on the allowed leakage current: Ileakages less than 10xe2x88x924 A/cm2.
Thus, there is a continuous need for improved memory capacitor designs and improved methods of on-chip capacitor fabrication to maintain capacitance values despite continued reductions in capacitor area and minimum node dielectric layer thickness limits.
The present invention provides an improved node dielectric layer for an on-chip capacitor and method of fabricating the layer which increases its performance. In particular, the present invention includes a Free Radical Enhanced Rapid Thermal Oxidation (FRE RTO) step while forming the node dielectric layer of an on-chip capacitor instead of a furnace oxidation step to produce a cleaner oxide than the furnace oxide. The cleaner oxide formed by the FRE RTO step results in a higher energy barrier between the electrodes and the node dielectric layer which results in lower leakage and higher performance. Other specific embodiments of the invention include: a Low Pressure Chemical Yapor Deposition (LPCVD) of SiN step; a nitridation step, done by either Remote Plasma Nitridation (RPN), Rapid Thermal Nitridation (RTN), Decoupled Plasma Nitridation (DPN) or other nitridation method; selective oxidation; deposition of a metal layer; and selective oxidation of the metal layer. Combinations of these various process steps of forming a node dielectric layer improve the layer quality and, thus, the performance of the node dielectric layer. The improved dielectric layer, therefore, increases the capacitance of the on-chip capacitor without a substantial increase in the leakage current. Alternatively, the improved dielectric layer decreases the leakage without a decrease in the capacitance.
The foregoing and other features and advantages of the present invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.